P R E L I M I N A R Y
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
RESET# = V
(Note 1)
ID
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
Perform Erase or
Program Operations
RESET# = V
IH
tional writes when VCC is greater than VLKO
.
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
20514C-5
Logical Inhibit
Notes:
1. All protected sectors unprotected.
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
2. All previously protected sectors are protected once
again.
Power-Up Write Inhibit
Figure 1. Temporary Sector Unprotect Operation
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
Am29LV400
12
CYPRESS [ CYPRESS ]
