P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
3.3 V
-90R,
-100
-120,
-150
Test Condition
Output Load
Unit
2.7 kΩ
Device
Under
Test
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
20514C-14
Figure 10. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
20514C-15
Figure 11. Input Waveforms and Measurement Levels
25
Am29LV400
CYPRESS [ CYPRESS ]
