P R E L I M I N A R Y
Figure 20, Alternate CE Controlled Write Operation
cycle endurance is minimum, not typical. Revised Note
1 to include write endurance; moved Note 1 references
in table to table head. Consolidated and moved Note 1
and Note 3 references in table to table head. Combined
Note 2 and Note 5 into new Note 1, which applies to the
entire table; revised to indicate that DQ5=1 after any
maximum time. Comments for program and erase now
straddle parameter rows. Separated the two sentences
in Note 4 into new Notes 4 and 5; added corresponding
note references to comment section.
Timings:
Changed 5555H to 555H in addresses waveform to
match command definitions (Table 5).
Erase and Programming Performance:
Added typical chip erase specification. Renamed
erase/program cycles specification to erase/program
endurance. Corrected to indicate 1,000,000 cycle en-
durance is typical, not maximum, and that 100,000
Am29LV008T/Am29LV008B
39