P R E L I M I N A R Y
ecuting (RY/BY pin is high), the reset operation will be
RESET: Hardware Reset Pin
complete within 500 ns.
The RESET pin is an active low signal. A logic ‘0’ on
this pin will force the device out of any mode that is cur-
rently executing back to the reset state. This allows a
system reset to take effect immediately without having
to wait for the device to finish a long execution cycle.To
avoid a potential bus contention during a system reset,
the device is isolated from the data I/O bus by tri-stating
the data output pins for the duration of the RESET
pulse.
Asserting RESET during a program or erase operation
leaves erroneous data stored in the address locations
being operated on at the time of device reset.These lo-
cations need updating after the reset operation is com-
plete. See Figure 2 for timing specifications.
The device enters I
standby mode (200 nA) when
CC4
V
± 0.3V is applied to the RESET pin.The device can
SS
enter this mode at any time, regardless of the logical
condition of the CE pin. Furthermore, entering I
If RESET is asserted during a program or erase oper-
ation, the RY/BY pin will remain low until the reset op-
eration is internally complete.This will require between
1 µs and 20 µs. Hence the RY/BY pin can be used to
signal that the reset operation is complete. Otherwise,
allow for the maximum reset time of 20 µs. If RESET is
asserted when a program or erase operation is not ex-
CC4
during a program or erase operation leaves erroneous
data in the address locations being operated on at the
time of the RESET pulse. These locations need updat-
ing after the device resumes standard operations. After
the RESET pin goes high, a minimum latency period of
50 ns must occur before a valid read can take place.
tRL
RESET
RY/BY
tRRB
20511C-5
Figure 2. Device Reset During a Program or Erase Operation
tRP
RESET
RY/BY
0 V
20511C-6
Figure 3. Device Reset During Read Mode
Am29LV008T/Am29LV008B
19
CYPRESS [ CYPRESS ]
