P R E L I M I N A R Y
Data Protection
Write Pulse “Glitch” Protection
The Am29LV008 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. During power-up, the device automatically resets
the internal state machine to the read mode. Also, with
its control register architecture, alteration of the mem-
ory contents only occurs after successful completion of
the command sequences.
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = V , CE
IL
= V , or WE = V .To initiate a write, CE and WE must
IH
IH
be logical zero while OE is a logical one.
Power-Up Write Inhibit
The Am29LV008 incorporates several features to pre-
Power up of the device with WE = CE = V and OE =
IL
vent inadvertent write cycles resulting from V
CC
V
will not accept commands on the rising edge of WE.
IH
power-up and power-down transitions or system noise.
The internal state machine is automatically reset to
read mode on power up.
Low V Write Inhibit
CC
To avoid initiation of a write cycle during V power-up
CC
and power-down, a write cycle is locked out for V
CC
less than V
(lock-out voltage). If V
< V
, the
LKO
CC
LKO
command register is disabled and all internal program/
erase circuits are disabled. Under this condition, the
device will reset to read mode. Subsequent writes will
be ignored until the V level is greater than V
. It is
CC
LKO
the user’s responsibility to ensure that the control levels
are logically correct when V is above V
(unless
CC
LKO
the RESET pin is asserted).
20
Am29LV008T/Am29LV008B
CYPRESS [ CYPRESS ]
