P R E L I M I N A R Y
Table 5. Am29LV008 Command Definitions
Second Bus
Read/Write
Cycle
Fourth Bus
Read/Write
Cycle
Command
Sequence
Read/Reset
(Note 2)
Bus
Write
Cycles
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Req’d Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset/Read
1
3
XXX
555
F0
RA
RD
55
Autoselect
Manufacturer ID
AA
2AA
555
555
90
90
X00
X01
01
3E
Autoselect
Device ID
(Top Boot Block)
3
3
3
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
Autoselect
Device ID
(Bottom Boot Block)
555
555
90
90
X01
37
Autoselect
Sector Protect Verify
(Note 3)
00
01
SA
X02
Byte Program
Chip Erase
4
6
6
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
PD
AA
AA
555
555
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend
(Note 4)
1
1
XXX
XXX
B0
30
Erase Resume
(Note 5)
Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEor CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WEor CE pulse.
SA = Address of the sector to be erased or verified. Address bits A19–A13 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Table 1 for description of bus operations.
3. The data is 00h for an unprotected sector and 01h for a protected sector.The complete bus address is composed of the sector
address on A19–A13 and 02h on A7–A0.
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. Unless otherwise noted, address bits A19–A11 = X = don’t care.
bedded Program Algorithm. Upon executing the
Byte Programming
write command, the system is not required to pro-
The device is programmed on a byte-by-byte basis.
vide further controls or timing. The device will auto-
Programming is a four-bus-cycle operation. There
matically provide adequate internally generated
are two “unlock” write cycles. These are followed by
program pulses and verify the programmed cell
the program command and address/data write cy-
margin.
cles. Addresses are latched on the falling edge of
CE or WE, whichever occurs later, while the data is
latched on the rising edge of CE or WE, whichever
occurs first. The rising edge of CE or WE, whichever
occurs first, initiates programming using the Em-
The status of the Embedded Program Algorithm op-
eration can be determined three ways:
■ DATA Polling of DQ7
Am29LV008T/Am29LV008B
13
CYPRESS [ CYPRESS ]
