P R E L I M I N A R Y
USER BUS OPERATIONS
Read Mode
The Am29LV008 has three control functions which
must be satisfied in order to obtain data at the outputs:
s
CE is the power control and should be used for de-
vice selection (CE = V
IL
)
s
OE is the output control and should be used to gate
data to the output pins if the device is selected
(OE = V
IL
)
s
WE remains at V
IH
Address access time (T
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (T
CE
) is the delay from stable addresses
and stable CE to valid data at the output pins. The out-
put enable access time (T
OE
) is the delay from the fall-
ing edge of OE to valid data at the output pins
(assuming the addresses have been stable at least
T
ACC
– T
OE
time).
Deselecting CE (CE and RESET = V
CC
±
0.3 V) puts
the device into the I
CC3
standby mode. If the device is
deselected during an Embedded Algorithm operation,
it continues to draw active power (I
CC2
) prior to entering
the standby mode, until the operation is complete.
When the device is again selected (CE = V
IL
), active
operations occur in accordance with the AC timing
specifications.
Automatic Sleep Mode
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
c o n s u m p t i o n . T h i s i s ex t r e m e l y i m p o r t a n t i n
battery-powered applications. The Am29LV008 auto-
matically enables the low-power, automatic sleep
mode when addresses remain stable for 200 ns. Auto-
matic sleep mode is independent of the CE, WE, and
OE control signals. Typical sleep mode current draw is
200 nA (for CMOS-compatible operation). Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Standby Mode
The Am29LV008 is designed to accommodate low
standby power consumption by applying the following
voltages to the CE and RESET pins: I
CC3
for CMOS
compatible I/Os (current consumption <5
µ
A max.) is
enabled when a CMOS logic level ‘1’ (V
CC
±
0.3 V) is
applied to the CE control pin with RESET = V
CC
±
0.3
V. While in the I
CC3
standby mode, the data I/O pins re-
main in the high impedance state independent of the
voltage level applied to the OE input. See the DC Char-
acteristics section for more details on Standby Modes.
Output Disable
If the OE input is at a logic high level (V
IH
), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.
8
Am29LV008T/Am29LV008B
CYPRESS [ CYPRESS SEMICONDUCTOR ]
