D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29F400B Device Bus Operations
DQ8–DQ15
BYTE#
BYTE#
= VIL
Operation
CE#
L
OE# WE# RESET# A0–A17 DQ0–DQ7
= VIH
DOUT
DIN
Read
Write
L
H
L
H
H
AIN
AIN
DOUT
DIN
High-Z
High-Z
L
H
VCC
0.5 V
VCC
0.5 V
CMOS Standby
X
X
X
High-Z
High-Z
High-Z
TTL Standby
H
L
X
H
X
X
X
H
X
X
H
H
X
X
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
X
Output Disable
Hardware Reset
X
X
L
X
Temporary Sector Unprotect (See Note)
VID
AIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:See the sections onSector Group Protection and Temporary Sector Unprotect for more information.
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 9 for the timing diagram. I
DC Characteristics table represents the active current
specification for reading array data.
in the
CC1
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
Requirements for Reading Array Data
To read array data from the outputs, the system must
CE# to V , and OE# to V .
IL
IH
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
should remain at V . The BYTE# pin determines
IH
whether the device outputs array data in words or
bytes.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
8
Am29F400B
21505E8 November 11, 2009
CYPRESS [ CYPRESS ]
