D A T A S H E E T
proper signals to the control pins to prevent uninten-
Hardware Data Protection
tional writes when V is greater than V
.
CC
LKO
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Write cycles are inhibited by holding any one of OE# =
CC
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a
logical one.
Low V
Write Inhibit
CC
Power-Up Write Inhibit
When V
is less than V
, the device does not
LKO
CC
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
If WE# = CE# = V and OE# = V during power up, the
CC
IL
IH
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
device resets. Subsequent writes are ignored until V
CC
is greater than V
. The system must provide the
LKO
12
Am29F400B
21505E8 November 11, 2009
CYPRESS [ CYPRESS ]
