D A T A S H E E T
TEST CONDITIONS
Table 7. Test Specifications
All
5.0 V
Test Condition
-55
others
Unit
2.7 kΩ
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
5
100
20
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0–3.0 0.45–2.4
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
24
Am29F002B/Am29F002NB
21527D8 November 17, 2009
CYPRESS [ CYPRESS ]
