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AM29F002BB-90EK 参数 Datasheet PDF下载

AM29F002BB-90EK图片预览
型号: AM29F002BB-90EK
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 256KX8, 90ns, PDSO32, LEAD FREE, MO-142BBD, TSOP-32]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 40 页 / 1039 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号AM29F002BB-90EK的Datasheet PDF文件第15页浏览型号AM29F002BB-90EK的Datasheet PDF文件第16页浏览型号AM29F002BB-90EK的Datasheet PDF文件第17页浏览型号AM29F002BB-90EK的Datasheet PDF文件第18页浏览型号AM29F002BB-90EK的Datasheet PDF文件第20页浏览型号AM29F002BB-90EK的Datasheet PDF文件第21页浏览型号AM29F002BB-90EK的Datasheet PDF文件第22页浏览型号AM29F002BB-90EK的Datasheet PDF文件第23页  
D A T A S H E E T  
control the read cycles.) But DQ2 cannot distinguish  
DQ6: Toggle Bit I  
whether the sector is actively erasing or is erase-sus-  
pended. DQ6, by comparison, indicates whether the  
device is actively erasing, or is in Erase Suspend, but  
cannot distinguish which sectors are selected for era-  
sure. Thus, both status bits are required for sector and  
mode information. Refer to Table 6 to compare outputs  
for DQ2 and DQ6.  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete,  
or whether the device has entered the Erase Suspend  
mode. Toggle Bit I may be read at any address, and is  
valid after the rising edge of the final WE# pulse in the  
command sequence (prior to the program or erase  
operation), and during the sector erase time-out.  
Figure 5 shows the toggle bit algorithm in flowchart  
form, and the section “DQ2: Toggle Bit II” explains the  
algorithm. See also the DQ6: Toggle Bit I subsection.  
Refer to the Toggle Bit Timings figure for the toggle bit  
timing diagram. The DQ2 vs. DQ6 figure shows the dif-  
ferences between DQ2 and DQ6 in graphical form.  
During an Embedded Program or Erase algorithm  
operation, successive read cycles to any address  
cause DQ6 to toggle. (The system may use either OE#  
or CE# to control the read cycles.) When the operation  
is complete, DQ6 stops toggling.  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 toggles  
for approximately 100 μs, then returns to reading array  
data. If not all selected sectors are protected, the  
Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are  
protected.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 5 for the following discussion. When-  
ever the system initially begins reading toggle bit  
status, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, a  
system would noand store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has com-  
pleted the program or erase operation. The system can  
read array data on DQ7–DQ0 on the following read  
cycl.  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is erase-  
suspended. When the device is actively erasing (that is,  
the Embedded Erase algorithm is in progress), DQ6  
toggles. When the device enters the Erase Suspend  
mode, DQ6 stops toggling. However, the system must  
also use DQ2 to determine which sectors are erasing  
or erase-suspended. Alternatively, the system can use  
DQ7 (see the subsection on DQ7: Data# Polling).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the  
system also should note whether the value of DQ5 is  
high (see the section on DQ5). If it is, the system  
should then determine again whether the toggle bit is  
toggling, since the toggle bit may have stopped tog-  
gling just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
program or erase operation. If it is still toggling, the  
device did not complete the operation successfully, and  
the system must write the reset command to return to  
reading array data.  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling oce the Embedded  
Program algorithm is complete.  
The Write Operation Status tble shows the outputs for  
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit  
algorithm, and to the Toggle Bit Timings figure in the  
“AC Characteristics” section for the timing diagram.  
The DQ2 vs. DQ6 figure shows the differences  
between DQ2 and DQ6 in graphical form. See also the  
subsection on DQ2: Toggle Bit II.  
The remaining scenario is that the system initially  
determines that the toggle bit is toggling and DQ5 has  
not gone high. The system may continue to monitor the  
toggle bit and DQ5 through successive read cycles,  
determining the status as described in the previous  
paragraph. Alternatively, it may choose to perform  
other system tasks. In this case, the system must start  
at the beginning of the algorithm when it returns to  
determine the status of the operation (top of Figure 5).  
DQ2: Toggle Bit II  
The “Toggle Bit II” on DQ2, when used with DQ6, indi-  
cates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit  
II is valid after the rising edge of the final WE# pulse in  
the command sequence.  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.This is a failure  
condition that indicates the program or erase cycle was  
not successfully completed.  
DQ2 toggles when the system reads at addresses  
within those sectors that have been selected for era-  
sure. (The system may use either OE# or CE# to  
18  
Am29F002B/Am29F002NB  
21527D8 November 17, 2009  
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