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7KS0641DPHI02 参数 Datasheet PDF下载

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型号: 7KS0641DPHI02
PDF下载: 下载PDF文件 查看货源
内容描述: [HyperRAM™ Self-Refresh DRAM 3.0V/1.8V 64 Mb (8 MB)]
分类和应用: 动态存储器
文件页数/大小: 29 页 / 770 K
品牌: CYPRESS [ CYPRESS ]
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ADVANCE  
S27KL0641, S27KS0641  
Table 5.4 Configuration Register 0 Bit Assignments (Continued)  
CR0 Bit  
Function  
Settings (Binary)  
0000 - 5 Clock Latency  
0001 - 6 Clock Latency (default)  
0010 - Reserved  
0011 - Reserved  
0100 - Reserved  
...  
7-4  
Initial Latency  
1101 - Reserved  
1110 - 3 Clock Latency  
1111 - 4 Clock Latency  
0 - Variable Latency - 1 or 2 times Initial Latency depending on RWDS during  
CA cycles.  
1 - Fixed 2 times Initial Latency (default)  
3
2
Fixed Latency Enable  
Hybrid Burst Enable  
0: Wrapped burst sequences to follow hybrid burst sequencing  
1: Wrapped burst sequences in legacy wrapped burst manner (default)  
00 - 128 bytes  
01 - 64 bytes  
10- 16 bytes  
1-0  
Burst Length  
11 - 32 bytes (default)  
5.2.1.1  
Wrapped Burst  
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching the length of the  
configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes alignment and length. During wrapped  
transactions, access starts at the Command-Address selected location within the group, continues to the end of the configured word  
group aligned boundary, then wraps around to the beginning location in the group, then continues back to the starting location.  
Wrapped bursts are generally used for critical word first instruction or data cache line fill read accesses.  
5.2.1.2  
Hybrid Burst  
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing to the next half-  
page of data beyond the end of the wrap group. Continued access is in linear burst order until the transfer is ended by returning CS#  
high. This hybrid of a wrapped burst followed by a linear burst starting at the beginning of the next burst group, allows multiple  
sequential address cache lines to be filled in a single access. The first cache line is filled starting at the critical word. Then the next  
sequential line in memory can be read in to the cache while the first line is being processed.  
Table 5.5 CR0[2] Control of Wrapped Burst Sequence  
Bit  
Default Value  
Name  
Hybrid Burst Enable  
2
1
CR[2]= 0: Wrapped burst sequences to follow hybrid burst sequencing  
CR[2]= 1: Wrapped burst sequences in legacy wrapped burst manner  
Document Number: 001-97964 Rev. *E  
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