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7C419-30 参数 Datasheet PDF下载

7C419-30图片预览
型号: 7C419-30
PDF下载: 下载PDF文件 查看货源
内容描述: 五百一十二分之二百五十六/ 1K / 2K / 4K ×9异步FIFO [256/512/1K/2K/4K x 9 Asynchronous FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 22 页 / 512 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号7C419-30的Datasheet PDF文件第7页浏览型号7C419-30的Datasheet PDF文件第8页浏览型号7C419-30的Datasheet PDF文件第9页浏览型号7C419-30的Datasheet PDF文件第10页浏览型号7C419-30的Datasheet PDF文件第12页浏览型号7C419-30的Datasheet PDF文件第13页浏览型号7C419-30的Datasheet PDF文件第14页浏览型号7C419-30的Datasheet PDF文件第15页  
CY7C419/21/25/29/33  
Switching Waveforms (continued)  
ExpansionTiming Diagrams  
WRITE TO LAST PHYSICAL  
LOCATION OF DEVICE 1  
WRITE TO FIRST PHYSICAL  
LOCATION OF DEVICE 2  
W
t
WR  
t
t
XOH  
XOL  
[15]  
XO (XI )  
1
2
t
t
HD  
HD  
t
t
SD  
SD  
DATA VALID  
DATA VALID  
D D  
0
8
C42017  
READ FROM LAST PHYSICAL  
LOCATION OF DEVICE 1  
READ FROM FIRST PHYSICAL  
LOCATION OF DEVICE 2  
R
t
RR  
t
t
XOH  
XOL  
[15]  
XO (XI )  
1
2
t
HZR  
t
DVR  
t
t
DVR  
LZR  
DATA  
VALID  
DATA  
VALID  
Q Q  
0
8
t
A
t
A
C42018  
Note:  
15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).  
the read and write pointers is much less than the time that  
would be required for data propagation through the memory,  
which would be the case if the memory were implemented  
using the conventional register array architecture.  
Architecture  
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,  
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,  
4096 words of 9 bits each (implemented by an array of du-  
al-port RAM cells), a read pointer, a write pointer, control sig-  
nals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty  
flags.  
Resetting the FIFO  
Upon power-up, the FIFO must be reset with a Master Reset  
(MR) cycle. This causes the FIFO to enter the empty condition  
signified by the Empty flag (EF) being LOW, and both the Half  
Full (HF) and Full flags (FF) being HIGH. Read (R) and write  
Dual-Port RAM  
The dual-port RAM architecture refers to the basic memory  
cell used in the RAM. The cell itself enables the read and write  
operations to be independent of each other, which is neces-  
sary to achieve truly asynchronous operation of the inputs and  
outputs. A second benefit is that the time required to increment  
(W) must be HIGH tRPW/tWPW before and tRMR after the rising  
edge of MR for a valid reset cycle. If reading from the FIFO  
after a reset cycle is attempted, the outputs will all be in the  
high-impedance state.  
Document #: 38-06001 Rev. *A  
Page 11 of 22  
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