CY7C374i
[14]
Switching Characteristics Over the Operating Range
7C374i–66
7C374i–125 7C374i–100 7C374i–83 7C374iL–66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
[1]
t
t
Input to Combinatorial Output
10
13
12
15
15
18
20
22
ns
ns
PD
Input to Output Through Transparent Input or
PDL
[1]
Output Latch
t
Input to Output Through Transparent Input
and Output Latches
15
16
19
24
ns
PDLL
[1]
[1]
t
t
Input to Output Enable
14
14
16
16
19
19
24
24
ns
ns
EA
ER
Input to Output Disable
Input Registered/Latched Mode Parameters
[9]
t
t
t
t
t
Clock or Latch Enable Input LOW Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
WL
WH
IS
[9]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
IH
Input Register Clock or Latch Enable to Com-
14
16
16
18
19
21
24
26
ICO
[1]
binatorial Output
t
Input Register Clock or Latch Enable to Out-
ns
ICOL
[1]
put Through Transparent Output Latch
Output Registered/Latched Mode Parameters
[1]
t
t
Clock or Latch Enable to Output
6.5
14
7
8
10
24
ns
ns
CO
S
Set-Up Time from Input to Clock or Latch En-
able
5.5
0
6
0
8
0
10
0
t
t
Register or Latch Data Hold Time
ns
ns
H
Output Clock or Latch Enable to Output Delay
16
19
CO2
[1]
(Through Memory Array)
t
t
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
12
12
15
15
20
ns
ns
SCS
SL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch En-
able
10
t
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
0
0
0
0
ns
HL
f
f
Maximum Frequency with Internal Feedback
125
100
143
83
66
MHz
MHz
MAX1
MAX2
[9]
(Least of 1/t
, 1/(t + t ), or 1/t
)
SCS
S
H
CO
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
158.3
125
100
+
WL
t
), 1/(t + t ), or 1/t
)
WH
S
H
CO
f
t
Maximum Frequency with External Feedback 83.3
(Lesser of 1/(t + t ) and 1/(t + t ))
76.9
0
67.5
0
50
0
MHz
ns
MAX3
CO
S
WL
WH
–t
Output Data Stable from Output Clock Minus
0
OH IH
[9, 15]
37x
Input Register Hold Time for 7C37x
Pipelined Mode Parameters
t
f
Input Register Clock to Output Register Clock
Maximum Frequency in Pipelined Mode
8
10
12
15
ns
ICS
125
100
83.3
66.6
MHz
MAX4
(Least of 1/(t
+ t ), 1/t , 1/(t
+ t ),
CO
IS
ICS
WL WH
1/(t + t ), or 1/t
)
IS
IH
SCS
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
7
CYPRESS [ CYPRESS ]
