CY7C372i
Capacitance
[9]
Parameter
C
I/O[11, 12]
C
CLK
Description
Input Capacitance
Clock Signal Capacitance
Test Conditions
V
IN
= 5.0V at f = 1 MHz
V
IN
= 5.0V at f = 1 MHz
5
Min.
Max.
8
12
Unit
pF
pF
Inductance
[9]
Parameter
L
Description
Maximum Pin Inductance
Test Conditions
V
IN
= 5.0V at f = 1 MHz
44-Lead CLCC
2
44-Lead PLCC
5
Unit
nH
Endurance Characteristics
[9]
Parameter
N
Description
Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Max.
100
Unit
Cycles
AC Test Loads and Waveforms
238Ω (com'l)
319Ω (mil)
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
170Ω (com'l)
236Ω (mil)
238Ω (com'l)
319Ω (mil)
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
3.0V
90%
GND
< 2 ns
10%
90%
10%
170Ω (com'l)
236Ω (mil)
(a)
(b)
ALL INPUT PULSES
Equivalent to:
THÉVENIN EQUIVALENT
99Ω (com'l)
136Ω (mil)
2.08V(com'l)
OUTPUT
2.13V(mil)
(c)
< 2 ns
Parameter
[13]
t
ER(–)
V
x
1.5V
V
OH
Output Waveform Measurement Level
0.5V
V
X
t
ER(+)
2.6V
V
0.5V
OL
V
X
t
EA(+)
1.5V
0.5V
V
X
V
OH
t
EA(–)
V
the
V
X
0.5V
V
OL
(d) Test Waveforms
Note:
11. C
I/O
for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISR
EN
is 15 pF Max.
12. C
I/O
for CLCC package is 15 pF Max.
13. t
ER
measured with 5-pF AC Test Load and t
EA
measured with 35-pF AC Test Load.
Document #: 38-03033 Rev. *A
Page 5 of 13
CYPRESS [ CYPRESS SEMICONDUCTOR ]
