CY7C1359A/GVT71256T18
Functional Block Diagram—256Kx18
[1]
HIGHER BYTE
WRITE
WEH#
BWE#
D
Q
D
LOWER BYTE
WRITE
Q
WEL#
GW#
CE#
CE2
CE2#
ZZ
OE#
ADSP#
MOE#
Power Down Logic
Latch
D
Q
lo byte write
hi byte write
ENABLE
D
Q
D
Q
D
Q
MATCH
Compare
DEN#
Latch
CLK
A
ADSC#
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
16
Address
Register
Input
Register
OUTPUT
REGISTER
256K x 9 x 2
SRAM Array
Output Buffers
D
Q
DQ1-
DQ18
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05120 Rev. **
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