Ultra37000 CPLD Family
Parameter[11]
VX
Output Waveform—Measurement Level
tER(–)
1.5V
V
OH
0.5V
0.5V
V
V
X
X
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthe
V
V
OL
X
V
OH
0.5V
V
X
0.5V
V
OL
(d) Test Waveforms
Switching Characteristics Over the Operating Range [12]
Parameter
Description
Unit
Combinatorial Mode Parameters
[13, 14, 15]
tPD
Input to Combinatorial Output
ns
ns
ns
ns
ns
[13, 14, 15]
[13, 14, 15]
tPDL
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
tPDLL
[13, 14, 15]
tEA
[11, 13]
tER
Input to Output Disable
Input Register Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[8]
Clock or Latch Enable Input HIGH Time[8]
ns
ns
ns
ns
ns
ns
Input Register or Latch Set-up Time
tIH
Input Register or Latch Hold Time
[13, 14, 15]
[13, 14, 15]
tICO
Input Register Clock or Latch Enable to Combinatorial Output
tICOL
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clocking Parameters
[14, 15]
tCO
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
ns
ns
ns
[13]
tS
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
Register or Latch Data Hold Time
tH
[13, 14, 15]
[13]
tCO2
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output ns
Delay (Through Logic Array)
tSCS
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
ns
[13]
tSL
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 ns
CLK1, CLK2, or CLK3) or Latch Enable
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
ns
Notes:
11. t measured with 5-pF AC Test Load and t measured with 35-pF AC Test Load.
ER
EA
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add t to this spec.
LP
14. Outputs using Slow Output Slew Rate, add t
to this spec.
SLEW
15. When V
= 3.3V, add t
to this spec.
CCO
3.3IO
Document #: 38-03007 Rev. *D
Page 17 of 64
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