Ultra37000 CPLD Family
Power Consumption
Typical 5.0V Power Consumption
CY37032
60
50
40
30
20
10
High Speed
Low Power
0
0
50
100
150
200
250
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
= 5.0V, T = Room Temperature
A
CC
CY37064
90
80
70
60
50
40
30
20
10
0
High Speed
Low Power
0
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 5.0V, T = Room Temperature
V
CC
A
Document #: 38-03007 Rev. *E
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