Ultra37000 CPLD Family
Switching Characteristics Over the Operating Range (continued)[12]
Parameter
Description
Unit
Product Term Clocking Parameters
[13, 14, 15]
tCOPT
tSPT
Product Term Clock or Latch Enable (PTCLK) to Output
ns
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
ns
ns
ns
tHPT
[13]
tISPT
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
tIHPT
Buried Register Used as an Input Register or Latch Data Hold Time
ns
ns
[13, 14, 15]
tCO2PT
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Pipelined Mode Parameters
[13]
tICS
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3)
ns
Operating Frequency Parameters
fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO
fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),
[5]
)
MHz
MHz
[5]
1/(tS + tH), or 1/tCO
)
[5]
fMAX3
fMAX4
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH
)
MHz
Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), MHz
[5]
or 1/tSCS
)
Reset/Preset Parameters
tRW
Asynchronous Reset Width[5]
ns
ns
ns
ns
ns
ns
[13]
tRR
Asynchronous Reset Recovery Time[5]
Asynchronous Reset to Output
Asynchronous Preset Width[5]
[13, 14, 15]
tRO
tPW
[13]
tPR
Asynchronous Preset Recovery Time[5]
[13, 14, 15]
tPO
User Option Parameters
Asynchronous Preset to Output
tLP
Low Power Adder
ns
ns
ns
tSLEW
t3.3IO
Slow Output Slew Rate Adder
3.3V I/O Mode Timing Adder[5]
JTAG Timing Parameters
tS JTAG
tH JTAG
tCO JTAG
fJTAG
Set-up Time from TDI and TMS to TCK[5]
Hold Time on TDI and TMS[5]
Falling Edge of TCK to TDO[5]
Maximum JTAG Tap Controller Frequency[5]
ns
ns
ns
ns
Document #: 38-03007 Rev. *D
Page 18 of 64
CYPRESS [ CYPRESS ]
