Ultra37000 CPLD Family
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface applications. Bus-hold additionally allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connec-
tions to VCC or GND. For more information, see the application
note Understanding Bus-Hold—A Feature of Cypress CPLDs.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
I/O MACROCELL
FAST
FROM PTM
0
1
SLEW
C26
SLOW
0−16
PRODUCT
TERMS
C25
I/O CELL
0
1
O
O
0
1
P
D/T/L
Q
0
1
2
3
4
“0”
“1”
0
O
R
C4
1
2
3
O
DECODE
C2 C3
C0 C1C24
C6 C5
1
0
BURIED MACROCELL
FROM PTM
0−16
0
1
PRODUCT
TERMS
C25
0
1
0
O
O
P
D/T/L
1
Q
0
1
Q
2
3
C7
R
4
DECODE
C2 C3
C0 C1C24
1
0
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
ASYNCHRONOUS
BLOCK RESET
ASYNCHRONOUS
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
OE0
OE1
BLOCK PRESET
Figure 2. I/O and Buried Macrocells
Document #: 38-03007 Rev. *D
Page 5 of 64
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