Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37512V
2 5 0
2 0 0
1 5 0
1 0 0
5 0
H ig h S p e e d
L o w P o w e r
0
0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
= 3.3V, T = Room Temperature
A
CC
Pin Configurations[20]
44-pin TQFP (A44)
Top View
44 43 42 41 40 39 38 37 36 35 34
I/O /TDI
27
1
I/O /TCK
5
33
I/O
6
I/O
26
32
31
2
3
4
5
6
I/O
7
I/O
25
I/O
24
CLK /I
30
29
28
27
2
0
JTAG
CLK /I
EN
GND
4
1
GND
I
3
CLK /I
7
1
8
0
CLK /I
I/O
26
25
24
23
8
9
3
2
I/O
23
I/O
22
I/O
9
I/O
10
I/O
11
10
11
I/O
21
12 13 14 15 16 17 18 19 20 21 22
Document #: 38-03007 Rev. *D
Page 31 of 64
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