CY7C375i
Pin Configurations (continued)
PGA
Bottom View
R
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
109
106
105
102
100
112
115
113
111
107
103
118
116
114
CC
121
119
117
123
122
120
126
125
124
CC
127
0
3
5
6
8
7
9
10
13
11
14
I/O
I/O
GND
I/O
I/O
I/O
I/O
110
1
4
15
17
16
19
108
N
ISR
EN
GND
GND
2
12
/SDI
I/O
/SCLK
M
20
I/O
V
V
GND
V
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
104
101
CC
18
21
24
22
25
27
30
31
32
34
36
38
41
42
45
L
I/O
I/O
I/O
I/O
23
26
29
K
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
98
96
95
94
91
89
86
83
80
78
99
97
CLK
/I
3
J
H
G
V
V
CLK
28
CC
CC
4
CLK
/I
CLK
0
2
GND
GND
GND
GND
/I
3
0
CLK1
/I1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
I/O
I/O
93
90
87
84
81
79
75
92
88
85
82
CC
CC
33
35
37
40
44
46
48
F
E
GND
I/O
I/O
I/O
I/O
39
43
47
49
51
D
C
V
GND
V
CC
GND
I/O
V
CC
CC
76
I/O
I/O
GND
I/O
I/O
I
I/O
I/O
56
I/O
I/O
GND
72
70
69
66
65
64
2
60
61
62
53
55
57
50
/SDO
I/O
/
52
B
A
I/O
I/O
I/O
GND I/O
I/O
I/O
I/O
I/O
77
74
73
71
68
67
58
59
SMODE
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
I/O
9
I/O
I/O
13
I/O
14
63
71
1
8
10
11
12
15
7C375i–4
Logic Block
Functional Description (continued)
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Product Term Array
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
Like all members of the FLASH370i family, the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 128 I/O pins on the CY7C375i.
In addition, there is one dedicated input and four input/clock
pins.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C375i remain the same.
Document #: 38-03029 Rev. **
Page 4 of 17
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