STK12C68
STK12C68-M SMD#5962-94599
8K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• 25ns, 45ns and 55ns Access Times
• “Hands-off” Automatic
STORE
with External
68μF Capacitor on Power Down
•
STORE
to Nonvolatile Elements Initiated by
Hardware, Software or
AutoStore™
on Power
Down
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to Nonvolatile Ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in Nonvolatile Ele-
ments (Commercial/Industrial)
• Commercial, Industrial and Military Tempera-
tures
• 28-Pin SOIC, DIP and LCC Packages
DESCRIPTION
The Simtek STK12C68 is a fast static
RAM
with a
nonvolatile element incorporated in each static
memory cell. The
SRAM
can be read and written an
unlimited number of times, while independent, non-
volatile data resides in Nonvolatile Elements. Data
transfers from the
SRAM
to the Nonvolatile Elements
(the
STORE
operation) can take place automatically
on power down. A 68μF or larger capacitor tied from
V
CAP
to ground guarantees the
STORE
operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the Nonvolatile
Elements to the
SRAM
(the
RECALL
operation) take
place automatically on restoration of power. Initia-
tion of
STORE
and
RECALL
cycles can also be soft-
ware controlled by entering specific read
sequences. A hardware
STORE
may be initiated with
the HSB pin.
BLOCK DIAGRAM
V
CCX
V
CAP
POWER
CONTROL
PIN CONFIGURATIONS
V
CAP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
QUANTUM TRAP
128 x 512
A
5
ROW DECODER
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
STORE/
RECALL
CONTROL
HSB
V
CCX
W
HSB
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - LCC
SOFTWARE
DETECT
A
0
- A
12
28 - DIP
28 - SOIC
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
PIN NAMES
A
0
- A
12
DQ
0
-DQ
7
E
W
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
G
HSB
V
CCX
V
CAP
V
SS
March 2006
1
Document Control # ML0008 rev 0.5
CYPRESS [ CYPRESS SEMICONDUCTOR ]
