STK12C68-5 (SMD5962-94599)
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [23]
35 ns
55 ns
Max
Parameter
Alt
Description
Unit
Min
35
0
Max
–
Min
55
0
[21]
tRC
tAVAV
tAVEL
tELEH
tELAX
STORE/RECALL initiation cycle time
Address setup time
–
–
ns
ns
ns
ns
s
[22]
tSA
–
[22]
tCW
Clock pulse width
25
20
–
–
30
20
–
–
[22]
tHACE
Address hold time
–
–
tRECALL
RECALL duration
20
20
Switching Waveform
Figure 13. CE Controlled Software STORE/RECALL Cycle [23]
tRC
tRC
ADDRESS # 1
ADDRESS # 6
ADDRESS
tSA
tSCE
CE
tHACE
OE
t
STORE / tRECALL
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA)
Notes
21. CE and OE low for output behavior.
22. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
23. The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51026 Rev. *C
Page 13 of 18
CYPRESS [ CYPRESS ]
