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5962-8872502XX 参数 Datasheet PDF下载

5962-8872502XX图片预览
型号: 5962-8872502XX
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX1, 45ns, CMOS, CQCC28, CERAMIC, LCC-28]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 11 页 / 145 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
MT5C2561
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
4.
5.
6.
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition, t
HZCE
is
less than t
LZCE
, and t
HZWE
is less than t
LZWE
and t
HZOE
is
less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
900
µA
CONDITIONS
SYM
V
DR
MIN
2
MAX
---
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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