CY7C199
[3, 7]
Switching Characteristics Over the Operating Range
7C199-8
7C199-10
Min. Max.
7C199-12
Min. Max.
7C199-15
Min. Max.
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
8
3
10
3
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
8
10
12
15
AA
Data Hold from Address Change
CE LOW to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
8
10
5
12
5
15
7
OE LOW to Data Valid
4.5
[8]
OE LOW to Low Z
0
3
0
0
3
0
0
3
0
0
3
0
[8, 9]
OE HIGH to High Z
5
4
8
5
5
5
5
7
7
[8]
CE LOW to Low Z
[8,9]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
15
PD
[10, 11]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
8
7
7
0
0
7
5
0
10
7
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
9
0
0
HA
0
0
0
SA
7
8
9
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
8
9
0
0
0
HD
[9]
WE LOW to High Z
5
6
7
7
HZWE
LZWE
[8]
WE HIGH to Low Z
3
3
3
3
Shaded area contains preliminary information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WEcontrolled, OE LOW) is the sum of tHZWE and tSD
.
5
CYPRESS [ CYPRESS ]
