Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT B CLOCK
tCHMCLK
tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE
ALMOST EMPTY FLAG
(active LOW)
tCHMSKEW3
tCHMFO
tCHMFO
PORT A CLOCK
READ ENABLE
tCHMFH
tCHMFS
PORT B CLOCK
tCHMCLK
WRITE ENABLE
tCHMFO
tCHMFO
PROGRAMMABLE
ALMOST FULL FLAG
(Active LOW)
tCHMSKEW3
PORT A CLOCK
READ ENABLE
Document #: 38-03039 Rev. *H
Page 36 of 86