CCLD-023 5x7mm SMD
LVDS Clock Oscillator
PART NUMBER GUIDE
CCLD - 023 X - 50 - 155.520
#1
#2 #3
#4
#5
#1 Crystek LVDS Osc.
#2 Model 023
Stability Indicator
Blank(std) ±100ppm
#3 Temp. Range (Blank=0/70°C)(M=-20/70°C)(X=-40/85°C)
#4 Stability: (see Table 1)
#5 Frequency in MHz: 3 or 6 decimal places
50
25
20
±50ppm
±25ppm
±20ppm
Example:
CCLD-023X-50-155.520
2.5V, -40/85°C, ±50ppm, 155.520 MHz
Table 1
RECOMMENDED REFLOW SOLDERING PROFILE
Mechanical:
Ramp-Up
Critical
3°C/Sec Max.
Temperature Zone
Shock: MIL-STD-883, Method 2002, Condition B
Solderability: MIL-STD-883, Method 2003
Vibration: MIL-STD-883, Method 2007, Condition A
Solvent Resistance: MIL-STD-202, Method 215
260°C
Ramp-Down
6°C/Sec.
217°C
200°C
150°C
Resistance to Soldering Heat: MIL-STD-202, Method 210, Condition I or J
Preheat
90 Secs. Max.
180 Secs. Max.
8 Minutes Max.
Environmental:
Thermal Shock: MIL-STD-883, Method 1011, Condition A
Moisture Resistance: MIL-STD-883, Method 1004
260°C for
10 Secs. Max.
NOTE: Reflow Profile with 240°C peak also acceptable.
0.274 ±0.007
(6.96 ±0.18)
Tri-State Function
Pin #1
State
Output
State
Part Number
Frequency
DC Lot Code
0.193 ±0.007
(4.90 ±0.18)
0.045 ±0.008
(1.14 ±0.20)
Open or N/C
Active
“1” level 0.7*Vcc Min Active
“0”level 0.3*Vcc Max High Z
Denotes pad 1
SUGGESTED PAD LAYOUT
0.055 Typ
(1.40 Typ)
0.071 SQ
(1.80)
Pad Connection
0.045 ±0.008
(1.14 ±0.20)
1
2
3
4
5
6
Enable/Disable
N/C
#1
#6
#2
#5
#3
#4
0.148
(3.75)
GND
Out
0.100
(2.54)
Comp. Out
VCC
0.200
(5.08)
0.200
(5.08)
0.01uF Bypass Capacitor Recommended
Rev.: C
Date: 10-10-07