RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.6 PCM Formatter
7
6
5
4
3
2
1
0
RFRAME_LOC[7:0]
0xC4—RSER Frame Bit Location (RFRAME_LOC_HI)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
RFRAME_LOC[8]
RFRAME_LOC[8:0] RSER Frame Bit Location—Establishes the number of PCM bit delays, in the range of 1 bit to
512 bits, from the internal PCM receive timebase’s output of bit 0 to the rising edge of
RMSYNC. Due to internal bit delays, a value of two will delay RMSYNC by one RCLK
period, in which case the rising edge of RMSYNC coincides with output of RSER bit 1. If the
system desires RMSYNC to mark RSER bit0, then RFRAME_LOC is programmed to equal 1.
The following examples assume RMSYNC is desired to mark RSER bit 0:
PCM Frame Length
E1 = 256 bits
T1 = 193 bits
64x64 = 512 bits
RFRAME_LOC[8:0] = Decimal (hex)
1 (0x01)
1 (0x01)
1 (0x01)
0xC5—RSER Multiframe Bit Location (RMF_LOC)
7
6
5
4
3
2
1
0
—
—
RMF_LOC[5:0]
RMF_LOC[5:0]
RSER Multiframe Bit Location—Establishes the number of PCM frame delays, in the range of
1 to 64 frames, from the internal PCM receive timebase’s output of frame 0 to the rising edge
of RMSYNC. Due to internal frame delay, a value of one delays RMSYNC by one PCM
frame. RMF_LOC enacts the RMSYNC frame delay after the RFRAME_LOC bit delay. If the
system desires RMSYNC to mark RSER frame 0, then RMF_LOC is programmed to equal 0.
The following examples assume RMSYNC is desired to mark RSER frame 0:
PCM Multiframe Length
E1 = 16 frames
RMF_LOC[5:0] = Decimal (hex)
0 (0x00)
0 (0x00)
0 (0x00)
SF = 12 frames
ESF = 24 frames
0xC6—PCM Multiframe Length (MF_LEN)
7
6
5
4
3
2
1
0
—
—
MF_LEN[5:0]
N8953BDSB
Conexant
4-27
CONEXANT [ CONEXANT SYSTEMS, INC ]
