RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.5 HDSL Channel
3.5 HDSL Channel
The three identical HDSL channels (CH1, CH2, and CH3) consist of separate
transmit and receive circuits that are responsible for the assembly of HDSL output
frames and the disassembly of HDSL receive frames. The basic structure of an
HDSL frame is shown in Table 3-2. Each frame is nominally 6 ms in length and
consists of 48 payload blocks with each block containing a single Z-bit, plus an
application-specific number of payload bytes. The MPU selects the desired
payload block length in HFRAME_LEN [addr 0xCA], in which the length is
programmed to equal the number of payload and Z-bits. Groups of 12 payload
blocks are concatenated and separated by an ordered set of HDSL overhead bits,
in which a 14-bit SYNC word pattern identifies the starting location of the HDSL
frame. 50 overhead bits are defined in one HDSL frame, but the last 4 STUFF
(sq1–sq4) bits are nominally present in alternate frames. Therefore, one frame
contains an average of 48 overhead bits.
N8953BDSB
Conexant
3-19
CONEXANT [ CONEXANT SYSTEMS, INC ]
