RS8953B/RS8953SPB
1.0 HDSL Systems
HDSL Channel Unit
1.1 HTU Applications
1.1.4 Loop Carrier/Pair Gain
Figure 1-5 shows a channel bank application where the PCM channel connects a
bank of voice and/or data subscriber line interfaces using an Nx64 bus. The total
number of subscriber lines determines the PCM channel rate and determines how
many HDSL wire pairs are needed to transport the application up to the digital
loop carrier, cellular base station, network distribution element, or to the private
branch exchange. The RS8953B supplies the PCM frame sync reference and acts
as the PCM bus master for the remote channel bank. The RS8953B’s Digital
Phase Locked Loop (DPLL) clock recovery allows PCM channel rates down to
2x64 or 128 kpbs. Unpopulated PCM timeslots or HDSL payload bytes can be
replaced by an 8-bit programmable fixed pattern, or one of four Pseudo-Random
Bit Sequence (PRBS) patterns.
Figure 1-5. Voice (Pairgain/Cellular/PCS) System Block Diagram
Nx64
Bus
Loop, Access,
or Distribution
Node
SLI
1
CH1
RS8953B
CH2
CH3
Optional
SLI
n
NOTE(S): SLI = Subscriber Line Interface
N8953BDSB
Conexant
1-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
