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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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B
Appendix B: Bt8953A/RS8953B  
Product Bulletin  
B.1 BCLK Phase Constraints In Repeater Mode;  
Non-Conformance Product Affected: Bt8953A and  
RS8953B  
While in repeater mode (REPEAT_EN = 1 for CH1 and CH2), a BCLK1 to  
BCLK2 phase difference of 180 degrees, +/- 5 nSec, will result in corrupted data  
transfer. All other phase relationships are acceptable.  
In a repeater mode application, to prevent a phase difference of 180 degrees  
between BCLK1 and BCLK2, the same clock is feed to both BCLK1 and  
BCLK2. To use the same clock for both HDSL transceivers, one HDSL  
transceiver needs to be slaved to the other HDSL transceiver. This is  
accomplished by setting the HDSL transceiver, which is configured as HTU-C, to  
“parallel slave mode.” Then the parallel signals from the HDSL transceiver need  
to be externally converted to “serial, sign first mode” to interface to the  
Bt8953A/RS8953B.  
To configure the ZipWire transceiver to “parallel slave mode”, address 0x06  
of the ZipWire transceiver needs to be modified. Also to align the sign and  
magnitude data correctly, the tbclk_pol and rbclk_pol need to set properly. The  
tbclk_pol and rdbclk_pol are controlled by address 0x06 of the ZipWire  
transceiver. TQ[1,0] should be sampled on the falling edge of TBCLK. RQ[1,0]  
should be updated on the falling edge of RBCLK.  
N8953BDSB  
Conexant  
B-1  
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