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System Architecture
Hardware Interface
A system block diagram is shown in Figure 1.
The major interface signals are shown in Figure 2.
5&'86%
MODEM DEVICE SET
TELEPHONE
LINE
TEL HANDSET
HEADPHONE/
SPEAKER
MICROPHONE
USB
INTERFACE
USB
CONTROLLER
UNIT
(UCU)
[68-PIN PLCC]
(R8292/
80931AA)
MICRO
CONTROLLER
UNIT
(MCU)
[80-PIN PQFP]
(L2800)
MODEM
DATA PUMP
(MDP)
[100-PIN PQFP]
(R6764)
TELEPHONE
LINE/
TELEPHONE
HANDSET/
AUDIO
INTERFACE
CIRCUIT
32K x 8
ROM
1M (128K x 8)
RAM
2M (256K x 8)
ROM/FLASH ROM
MD234F1 BD
Figure 1. Block Diagram
~RINGWAKE
~RLY1 (~OH)
~RLY2 (~VOICE)
XTAL1
CRYSTAL
CIRCUIT
XTAL2
CRYSTAL
CIRCUIT
XTLI
XTLO
~RLY3 (~MUTE)
~RLY4 (~CALLID)
~EXTOH
LCS
TELEPHONE
LINE
TELEPHONE
LINE/
TELEPHONE
HANDSET/
AUDIO
INTERFACE
CIRCUIT
VCC
RINGD
VD3.3
SVCC
CLKOUT
~WKRESOUT
DPIRQ
D+
USB
D-
USB
CONTROLLER
UNIT
(UCU)
A0-A15
D0-D7
A0-A2
D0-D7
MICRO
CONTROLLER
UNIT
(MCU)
~READ
~WRITE
A0-A17
D0-D7
~DPSEL
~ROMSEL
~RAMSEL
DGND, AGND
~READ
~WRITE
A0-A4
D0-D7
TELEPHONE
HANDSET
MICROPHONE
HEADPHONE/
SPEAKER
VDD
CLKIN
~WKRES
IRQ
MODEM
DATA
PUMP
(MDP)
RS0-RS4
RIN
TXA1
TXA2
TELIN*
TELOUT*
SPKM
MICV*
MICM**
~DPSEL
~CS
~RES1
~RES2
VGG
AVDD
VAA
~RESET
SVCC (+5V)
SVCC (+5V)
SVCC (+5V)
A0-A17
SVCC (+5V)
VDD
~WRITE
DGND
~ROMSEL
A0-A16
D0-D7
A0-A15
D0-D7
~READ
32K X 8
~READ
~WRITE
~RAMSEL
MD234F2 IF
1M (128K X 8)
* SP MODEL.
** NON-SP MODEL.
EXTERNAL
BUS
D0-D7
~READ
2M (256K X 8)
ROM/
FLASH ROM
RAM
ROM
Figure 2. Hardware Interface Signals
0'
CONEXANT [ CONEXANT SYSTEMS, INC ]
