2.0 Hardware Interface
RC224ATL/224ATLV
2.1 Hardware Interface
EmbeddedModem Family
Line Status Register
(Addr = 5)
The LSR, an 8-bit register, provides status information to the host concerning data
transfer.
7
6
5
4
3
2
1
0
0
TEMT
THRE
BI
FE
PE
OE
DR
Bit 7:
This bit is set to logic 0.
TEMT
THRE
Transmitter Empty. This bit is set to a logic 1 whenever the
Transmitter Holding Register (THR) and the Transmitter Shift
Register (TSR) are both empty. It is reset to a logic 0 whenever
either the THR or TSR contains a data character.
Transmitter Holding Register Empty. This bit indicates that
the modem is ready to accept a new character for
transmission. In addition, this bit causes the modem to issue
an interrupt to the host when the Transmit Holding Register
Empty Interrupt Enable bit (IIR1) is set to logic 1. The THRE
bit is set to a logic 1 when a character is transferred from the
Transmitter Holding Register into the Transmitter Shift
Register. The bit is reset to logic 0 concurrently with the
loading of the Transmitter Holding Register by the host.
BI
Break Interrupt. This bit is set to a logic 1 whenever the
received data input is a space (logic 0) for longer than two full
word lengths plus 3 bits. The 81 indicator is reset whenever
the host reads the LSR.
FE
Framing Error. This bit indicates that the received character
did not have a valid stop bit. Bit 3 is set to a logic 1 whenever
the stop bit following the last data bit or parity bit is detected
as a zero bit. The FE bit is reset to a logic 0 whenever the host
reads the LSR.
PE
Parity Error. This bit indicates that the received data
character does not have the correct even or odd parity, as
selected by the Even Panty Select bit (LCR4) and the Stick
Parity bit (LCR5). The PE bit is set to a logic 1 upon detection
of parity error and is reset to a logic 0 whenever the host reads
the LSR.
OE
DR
Overrun Error. This bit indicates that data in the Receiver
Buffer Register was not read by the host before the next
character was transferred into the Receiver Buffer Register,
thereby destroying the previous character. The OE bit is reset
whenever the host reads the LSR.
Data Ready. This bit is set to a logic 1 whenever a complete
incoming character has been received and transferred into the
Receiver Buffer Register. Bit 0 is reset to a logic 0 when the
host reads the Receiver Buffer Register.
2-10
Conexant
D224ATLVDSC
CONEXANT [ CONEXANT SYSTEMS, INC ]
