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RC224ATLV 参数 Datasheet PDF下载

RC224ATLV图片预览
型号: RC224ATLV
PDF下载: 下载PDF文件 查看货源
内容描述: EmbeddedModem家庭 [EmbeddedModem Family]
分类和应用:
文件页数/大小: 104 页 / 1031 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Hardware Interface  
RC224ATL/224ATLV  
2.1 Hardware Interface  
EmbeddedModem Family  
Line Control Register  
(Addr = 3)  
The Line Control Register (LCR) specifies the format of the asynchronous data  
communications exchange.  
7
6
5
4
3
2
1
0
DLAB  
SB  
SP  
EPS  
PEN  
STB  
WLS1  
WLS0  
DLAB  
Divisor Latch Access Bit. This bit must be set to a logic 1 to  
access the Divisor latches of the baud generator during a read  
or write operation. It must be reset to a logic 0 to access the  
Receiver Buffer, the Transmitter Holding Register, or the  
Interrupt Enable Register.  
SB  
SP  
Set Break. When this bit is set to a logic 1, the transmit data is  
forced to the space (logic 0) state. The break is disabled by  
setting this bit to a logic 0. The Set Break bit acts only on the  
transmit data and has no effect on the serial in logic.  
Stick Parity. When stick parity is selected (LCR5 = 1), parity  
is enabled (LCR3 = 1), and even parity is selected (LCR4 = 1),  
the parity bit is transmitted and checked by the receiver as a  
logic 0. When stick parity is selected (LCR5 = 1), parity is  
enabled (LCR3 = 1), and odd parity is selected (LCR4 = 0),  
the parity bit is transmitted and checked by the receiver as a  
logic 1.  
EPS  
PEN  
STB  
Even Parity Select. When parity is enabled (LCR3 = 1), and  
Stick Parity (LCR5) is a logic 0, the number of logic 1s  
transmitted or checked in the data word bits and parity bit is  
either even (LCR4 = 1) or odd (LCR4 = 0).  
Parity Enable. When bit 3 is a logic 1, a parity bit is  
generated in the serial out (transmit) data stream and checked  
in the serial in (receive) data stream. The parity bit is located  
between the last data bit and the first stop bit.  
Number of Stop Bits. This bit specifies the number of stop  
bits in each serial out character. If bit 2 is a logic 0, one stop  
bit is generated regardless of word length. If bit 2 is a logic 1  
when either a 5-, 6-, 7-, or 8-bit word length is selected, two  
stop bits are generated. The serial in logic checks the first stop  
bit only regardless of the number of stop bits selected.  
WLS0 and WLS1 Word Length Select. These two bits specify the number of  
bits in each serial in or serial out character. The encoding of  
bits 0 and 1 is:  
Bit 1  
Bit 0  
Word Length  
5 Bits  
6 Bits  
7 Bits  
8 Bits  
0
0
1
1
0
1
0
1
2-8  
Conexant  
D224ATLVDSC  
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