RC224ATL/224ATLV
2.0 Hardware Interface
EmbeddedModem Family
2.1 Hardware Interface
Interrupt Identifier
Register (Addr = 2)
The Interrupt Identifier Register (IIR) identifies the existence and type of
prioritized pending interrupts. Four priority levels are set to assist interrupt
processing in the host.
When addressed during chip-select time, the IIR freezes the highest priority
interrupt pending and acknowledges no other interrupts until the particular
interrupt is serviced by the host.
7
6
5
4
3
2
1
0
0
0
0
0
0
PL1
PL0
IP
Bits 3-7:
PL0-1
Not used (always 0).
Highest Priority Pending Interrupt. These two bits identify
the highest priority pending interrupt.
Priority
2
1
Level
Pending Interrupt
1
1
0
1
0
1
(highest)
2
3
Receiver Line Status
Receiver Buffer Full
Transmitter Holding Register
Empty
0
0
4
Modem Status
IP
Interrupt Pending. When this bit is a logic 0, an interrupt is
pending. When this bit is a logic 1, no interrupt is pending.
This bit can be used in a hardwired prioritized or polled
environment to indicate whether an interrupt is pending. If an
interrupt is pending, the IIR contents can be used as a pointer
to the appropriate interrupt service routine in the host.
D224ATLVDSC
Conexant
2-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
