2.0 Hardware Interface
RC224ATL/224ATLV
2.1 Hardware Interface
EmbeddedModem Family
2.1 Hardware Interface
2.1.1 Parallel Interface
A 16450 UART-compatible parallel interface is provided.
Host Bus Interface
Eight data lines, three address lines, and four control lines are supported.
Interrupt Enable Register
(Addr=1, DLAB=0)
The Interrupt Enable Register (IER) enables four types of interrupts that can
separately assert the HINT output. A selected interrupt can be enabled by setting
the corresponding enable bit to a logic 1, or disabled by resetting the
corresponding enable bit to a logic 0. All interrupt sources are disabled by setting
bits 0–3 to a logic 0. Disabling all interrupts inhibits the Interrupt Identifier
Register (IIR) and inhibits assertion of the HINT output. All other system
functions operate normally, including the setting of the Line Status Register
(LSR) and the Modem Status Register (MSR).
7
6
5
4
3
2
1
0
0
0
0
0
EDSSI
ELSI
ETBEI
ERBFI
Bits 4-7:
EDSSI
Not used (always logic 0).
Enable Modem Status Interrupt. When this bit is a logic 1,
it enables assertion of the HINT output whenever bit 0, 1, 2, or
3 in the Modem Status Register (MSR) is a logic 1. When this
bit is a logic 0, it disables assertion of HINT due to setting of
any of these four MSR bits.
ELSI
Enable Receiver Line Status Interrupt. When this bit is a
logic 1, it enables assertion of the HINT output when any
receiver status bit in the Line Status Register (LSR); i.e., bits
1, 2, 3, or 4, changes state. When this bit is a logic 0, it
disables assertion of HINT due to change of the receiver LSR
bits.
ETBEI
ERBFI
Enable Transmitter Holding Register Empty Interrupt.
When this bit is a logic 1, it enables assertion of the HINT
output when the Transmitter Holding Register Empty (THRE)
bit in the Line Status Register (LSR5) is set to a logic 1. When
this bit is a logic 0, it disables assertion of HINT due to LSR5.
Enable Received Data Available Interrupt. When this bit is
a logic 1, it enables assertion of the HINT output when
received data is available in the Receiver Buffer; i. e., the Data
Ready bit in the Line Status Register (LSR0) is a logic 1.
When this bit is a logic 0, it disables assertion of HINT due to
the LSR0.
2-6
Conexant
D224ATLVDSC
CONEXANT [ CONEXANT SYSTEMS, INC ]
