2
2.0 Hardware Interface
Figure 2-1 and Figure 2-2 illustrate the RC224ATLV hardware interface signals
for the parallel and serial interfaces, respectively.
The RC224ATLV hardware interface signals are described in
Table 3-5, Hardware Interface Signal Definitions.
See Table 7-2, Timing–Host Bus Interface for a list of the host bus interface
timing parameters and Figure 7-1, Timing Waveform for an illustration of the
interface waveforms.
D224ATLVDSC
Conexant
2-1