Appendix C
CX28394/28395/28398
C.1 System Bus Compatibility
Quad/x16/Octal—T1/E1/J1 Framers
C.1.2 CHI Programming Options:
CMS = clock mode select
0 = line rate
1 = 2X line rate
XEN = transmitter enable
0 = disable (DX tri-stated)
1 = enable (DX driven during active time slots)
FE = frame edge select
0 = falling edge
1 = rising edge
XCE = CLKXR output edge select for DX
0 = falling edge
1 = rising edge
RCE = CLKXR input edge select for DR
0 = falling edge
1 = rising edge
XBOFF = 3-bit transmit output bit offset
000-1111 = CLKXR (or 2xCLKXR) delay from FS to DX bit0
RBOFF = 3-bit receive input bit offset
000-111 = CLKXR (or 2xCLKXR) delay from FS to DR bit0
XTS = 6-bit transmit output TS offset
00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DX bit0
RTS = 6-bit receive input TS offset
00-3F = CLKXR (or 2xCLKXR) TS delay from FS to DR bit0
The device only supports CHI and GCI buses if N = 24, 32, or 48, although
either bus is defined to operate at N x 64 from N = 4 to N = 48. The device does
not support AT&T's Dual CHI (separate A/B buses) or K2 buses, nor does it
support INTEL's SLD (ping/pong) 3-pin bus.
C-2
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
