4.0 Electrical/Mechanical Specifications
CX28394/28395/28398
4.6 System Bus Interface (SBI) Timing
Quad/x16/Octal—T1/E1/J1 Framers
Figure 4-18. SBI Timing—2048K Mode(1)
Transmit
TSBCKI
Receive
RSBCKI
(4)
RSYNCO
RSYNCI
TSYNCO
TSYNCI
Offset = 000 (TS0, Bit1)
(4)
RSYNCO
TSYNCO
(3)
(3)
Offset = 00B
(5)
TSYNCI
TSYNCO
TSYNCI
RSYNCI
RSYNCO
RSYNCI
Offset = 0FF
TS0
TS31
TS1
4
TS2
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
5 6 7 8 1 2 3 4
RPCMO
RSIGO
TPCMI
TSIGI
SIG31
SIG0
A B C D
SIG1
A B C D
A B C D
(2)
(2)
RINDO
TINDO
SIGFRZ
RSBCKI
RSYNCO
RSYNCI
RSYNCO
RSYNCI
TSBCKI
TSYNCO
TSYNCI
TSYNCO
TSYNCI
Offset = 000
(5)
Offset = 00B
NOTE(S):
(1)
(2)
(3)
(4)
(5)
Rising edge outputs and falling edge inputs shown. Refer to Table 4-21 for other edge combinations.
RINDO/TINDO programmed high or low on a per-time slot basis (SBCn; addr 0E0-0FF).
TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset.
Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6).
X2CLK control bit located in SBI_CR (addr 0D0).
4-20
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
