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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX28394/28395/28398  
2.0 Circuit Description  
Quad/x16/OctalT1/E1/J1 Framers  
2.4 Transmitter  
Multiframe Yellow Alarm  
Generation  
In E1 CAS framing modes, Multiframe Yellow Alarm is inserted into the transmit  
stream to alert far-end equipment that local received multiframe alignment is not  
recovered. E1 Multiframe Yellow Alarm is transmitted by setting the Y bit in time  
slot 16, frame 0.  
Transmission of Multiframe Yellow Alarm is controlled by these register bits:  
Bit Name  
Register  
INS_MYEL  
TMYEL  
AUTO_MYEL  
SRED  
[TFRM; addr 072]  
[TALM; addr 075]  
[TALM; addr 075]  
[ALM3; addr 049]  
Insertion of E1 Multiframe Yellow Alarm is controlled by INS_MYEL and  
inserted only when INS_MYEL is set. Multiframe Yellow Alarm generation can  
be initiated manually or automatically.  
Manual insertion of Multiframe Yellow Alarm is controlled by TMYEL.  
Setting this bit will unconditionally overwrite the Multiframe Yellow Alarm  
signal bit in the transmitted data stream.  
Automatic insertion of Multiframe Yellow Alarm is controlled by  
AUTO_MYEL in the TALM register. When set, the AUTO_MYEL mode will  
send yellow alarm for the duration of a receive loss of CAS multiframe alignment  
[SRED; addr 049]  
2.4.4.3 CRC Generation  
The CRC generation circuitry computes the value of the CRC6 code in T1 mode  
or the CRC4 code in E1 mode. Once computed, it is inserted into the appropriate  
position of the transmitted data stream. CRC overwrite is enabled by INS_CRC  
[TFRM; addr 072]. In T1 mode, CRC6 may be computed on only the payload  
data or on all data including the F-bit. Setting TINCF [TCR0; addr 070] selects  
CRC6 computation on all data.  
If the transmit frame format is configured as ESF and INS_CRC is active, the  
2 kbps CRC sequence is inserted. The position of the CRC-6 bits is shown in  
Table A-4, Extended Superframe Format.  
If the transmit frame format is configured as E1, and INS_CRC is active, the  
4 kbps CRC sequence is inserted. The position of the CRC-4 bits is shown in  
Table A-6, ITU–T CEPT Frame Format Time Slot 0 Bit Allocations.  
2.4.4.4 Far-End Block  
Error  
The register bits that control FEBE are INS_FE [TFRM; addr 072], TFEBE  
[TMAN; addr 074], FEBE_I [TMAN; addr 074], and FEBE_II [TMAN; addr  
074]. The Far-End Block Error (FEBE) generation circuitry inserts FEBE bits  
automatically or manually. Automatic FEBE generation is enabled by INS_FE. If  
the transmit frame format is configured as E1 and INS_FE bit is set, a FEBE is  
generated in response to an incoming CRC-4 error by setting an E-bit of TS0 to  
zero. Refer to Table A-6, ITU–T CEPT Frame Format Time Slot 0 Bit Allocations,  
for the location of the E-bits within the E1 frame.  
Generation  
Manual FEBE generation is enabled by TFEBE. If the transmit frame format  
is configured as E1 and TFEBE is set, the FEBE bits are supplied by the  
processor in FEBE_I and FEBE_II.  
100054E  
Conexant  
2-49