1.0 Pin Description
CX28331/CX28332/CX28333
1.1 Pin Assignments
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
Table 1-2. CX2833i-3x Pin Definitions (7 of 8)
Pin #
Signal Name
Description
I/O/P
Notes
CX28331-3x CX28332-3x CX28333-3x
58
—
—
—
81
44
—
81
58
REFCLK
REFCLK1
REFCLK2
Reference clock
for Ch1
I
Reference clock from off-chip.
This clock should be set to one of the
following:
Reference clock
for Ch2
I
I
•
•
•
E3 rate (34.368 MHz)
DS3 rate (44.736 MHz)
STS-1 rate (51.84 MHz)
—
—
44
REFCLK3
Reference clock
for Ch3
The clock rate should correspond to the
mode of operation that has been chosen for
the channel.
99
80
99
RBIAS
Bias resistor
Reset
O
A 12.1 kΩ ± 1% resistor tied from this pin
to ground provides the current reference to
the entire chip.(2)
97
96
97
96
97
96
Reset
GPD
I/O Asynchronous reset (reset entire device).
Global Power
down
I/O Power down (Static Idd testing).
0 = Power down disable
1 = Power down active
11
—
14
—
—
—
1
—
1
TMONP
Ch1 positive
input
I
I
Transmit monitor input pins are normally
tied to their respective transmit line
TMON1P
TMONM
TMON1M
TMON2P
outputs, i.e., (TMON1P
TMON1M TLINE1M).
TLINE1P and
—
4
—
4
Ch1 negative
input
Loss of signal outputs are active high
when the monitor inputs detect no signal.
The TX monitor test pin will assert all
TLOS outputs when TMONTST is high.
This is used to test board level functionality
downstream from the TLOS outputs.
21
11
Ch2 positive
input
I
I
—
—
—
24
—
—
14
21
24
TMON2M
TMON3P
TMON3M
Ch2 negative
input
Ch3 positive
input
I
Ch3 negative
input
I
59
—
—
—
80
45
—
80
59
TLOS
TX loss of signal
Ch1 Output
O
TLOS1
TLOS2
TX loss of signal
Ch2 Output
O
O
I
—
—
45
54
TLOS3
TX loss of signal
Ch3 Output
54
54
TMONTST
TX monitor test
pin
1-20
Conexant
100985A
CONEXANT [ CONEXANT SYSTEMS, INC ]
