CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
Table 1-21. Register Values for 640x480 / 800x600 / 1024x768 RGB In, SECAM-L Out (4 of 4)
640x480 RGB in,
800x600 RGB in, SECAM-L
SECAM-L out
1024x768 RGB in,
SECAM-L out
HOC = 12.72%
VOC = 12.15%
out HOC = 14.52%
HOC = 16.55%,
VOC=13.19%
VOC = 16.66%
CX25870 Register
Register Address
CX25870 Register Values
CX25870 Register Values
Values
0xCA
0xCC
C0
C0
24
C0
C0
24
C0
C0
24
0xCE(4)
0xD0
0xD2
0xD4
0xD6
0xD8
00
00
00
00
40
0
0
0
0
0
0
0
0
40
40
NOTE(S):
1. Register 0x6C contains the TIMING_RESET bit. Set this bit as your last programming step and the CX25870 will clear it
automatically later.
2. Register 0xC4 contains the EN_OUT bit. Adjust according to your design's interface as necessary.
3. Register 0xC6 contains the EN_BLANKO, EN_DOT, and IN_MODE[2:0] bits. Adjust according to your design's interface as
necessary.
4. Register 0xCE contains the OUT_MUXD[1:0], OUTMUXC[1:0], OUTMUXB[1:0], and OUTMUXA[1:0] bit fields for output
routing. Adjust according to your design's interface as necessary.
5. This is a SECAM specific register.
The procedure required to obtain a SECAM output with an overscan
compensation percentage that differs from those solutions in Table 1-21 is fairly
simple. First, configure the encoder so it generates a standard PAL-B output with
the desired overscan compensation percentage. This can be done through the use
of an autoconfiguration mode, a hand-generated, or a predefined register set.
Second, perform a full register read-back from the CX25870. Carefully note the
value for register 0xA2. Third, program only the bits found in Table 1-22 to their
new state within the CX25870.
Table 1-22. Vital SECAM Bit Settings–Register 0xA2
Bit Name
Location
State for PAL-BDGHI
State for SECAM
FM
Bit 7 of register 0xA2
Bit 5 of register 0xA2
Bit 3 of register 0xA2
0
1
0
1
0
0
PAL_MD
VSYNC_DUR
100381B
Conexant
1-73
CONEXANT [ CONEXANT SYSTEMS, INC ]
