1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.20 VGA Registers Involved in the TV Out Process
Timing constraints for the CX25870/871 are driven by the timing requirements of
the analog video output (NTSC, PAL, or SECAM) together with the active
resolution and overscan compensation ratio (i.e., amount of blanking in the active
region) of the television image. To explain what specific CRTC or VGA registers
within the graphics controller need to be involved in displaying a nonstandard or
desktop format on both a TV and CRT, one can work backwards from those
output signal timing requirements to determine the input timing requirements.
Each output field has a vertical blanking region and an active region. These
regions are defined relative to the vertical sync pulse, horizontal sync pulse, given
format (i.e., number of lines per field), and a given pixel clock frequency (i.e.,
number of pixel clocks per line). Within each line of the active region there is a
horizontal blanking period (that includes a horizontal sync pulse) and an active
period (where the image data is located). Given those parameters, at least six
registers within every generic graphics controller need to be changed for each
active/total resolution.
Table 1-17 lists VGA/CRTC Registers Involved in TV Out Process.
Table 1-17. VGA/CRTC Registers Involved in TV Out Process
Register Name
Description
Start VBLANK/VSYNC* and
End VBLANK/VSYNC*
These VGA registers work in combination with each other to control the scan line at which the
vertical blanking period begins and the point at which it ends.
VACTIVE
VTOTAL
Dictates the specific number of active lines for the present digital frame.
Specifies the number of scan lines from one VSYNC* active to the next VSYNC* active pulse.
The difference between Vtotal and Vactive is the amount of blanked lines.
HBLANK/HSYNC* Start
and
HBLANK/HSYNC* End
This VGA register set works in combination with each other to control the value of the pixel or
character clock counter where the HSYNC* signal becomes active and the position at which
HSYNC* becomes inactive.
HACTIVE
HTOTAL
Dictates the specific number of active pixels per line.
Specifies the number of pixel clocks or character clocks from one HSYNC* active to the next
HSYNC* active pulse. In other words, this is the total time required for both the displayed and
nondisplayed portions of a single scan line. The difference between Htotal and Hactive is the
amount of blanked pixels per line.
To achieve VGA compatibility, the controller must manipulate some of its own
VGA register settings in order to produce a hi-quality dual display on both the
computer monitor and TV. It should be noted that the encoder has no way of
knowing that a different VGA mode has been selected. As a result, it relies on the
I2C®-compatible master device to reconfigure it via an autoconfiguration mode
or complete register rewrite to make adjustments in its timing.
When the two devices are programmed correctly, regardless of the interface,
the required input HSYNC*/VSYNC* to first input active pixel or line spacing
“matches” the output HSYNC*/VSYNC* to first output active pixel or line
spacing. When this occurs, the graphics controller always transmits active data at
the time the CX25870/871 expects to receive it. Superior TV Out quality is
achieved only when this type of timing symmetry exists.
1-40
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
