CX25870/871
Appendix C Autoconfiguration Mode Register Values and Details
Flicker-Free Video Encoder with Ultrascale Technology
Table C-1. CX25870/871 Register Values for Autoconfiguration Modes 0–4 (3 of 3)
Autoconfiguration Mode #
0
1
2
3
4
0xB0
0xB2
00
80
20
8C
79
26
E8
A2
17
28
87
1F
00
80
20
0xB4
NOTE(S):
1. RGB digital input denotes that the CX25870/871 will be configured to receive the RGB default pixel input mode after an
autoconfiguration command which is 24-bit, RGB-multiplexed (i.e., IN_MODE[3:0] = 0000). If the desired RGB pixel input
mode is NOT 24-bit RGB-multiplexed, the CX25870/871's IN_MODE[3:0] bits must be programmed to the desired RGB pixel
input mode immediately before initiating a write to the CONFIG[5:0] bits.
2. YCrCb digital input denotes that the CX25870/871 will be configured to receive YCrCb pixel data after an autoconfiguration
command. The CX25870/871's IN_MODE[3:0] bits must be programmed to the desired YCrCb pixel input mode immediately
before initiating a write to the CONFIG[5:0] bits.
3. CX25870/871 registers not listed in this table (including IN_MODE[3:0]) do not get reprogrammed as a result of an
autoconfiguration command.
4. Pixel or Character signifies that this overscan ratio is acceptable for 8-clock per character graphics controllers or pixel-clock
controllers.
5. The CX25870/871 will be in master interface immediately after any autoconfiguration mode EXCEPT Mode 28 and Mode 29.
6. Mode 44 would ideally have 858 clocks per line. However, since 858 is not a multiple of 8, then 880 clocks per line was
utilized instead.
7. These autoconfiguration values assume a 13.500 MHz crystal resides between the XTALIN and XTALOUT pins. If the
14318_XTAL bit is set, then these autoconfiguration values will automatically change to reflect the presence of a 14.318 MHz
crystal.
100381B
Conexant
C-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
