CX25870/871
3.0 PC Board Considerations
Flicker-Free Video Encoder with Ultrascale Technology
3.8 Serial Interface
3.8 Serial Interface
3.8.1 Data Transfer on the Serial Interface Bus
Figure 3-16 illustrates the relationship between SID (Serial Interface Data) and
SIC (Serial Interface Clock) to be used when programming the internal registers
via the Serial Interface bus. If the bus is not being used, both SID and SIC lines
must be left high.
Every byte put onto the SID line should be 8 bits long (MSB first), followed
by an acknowledge bit, which is generated by the receiving device. Each data
transfer is initiated with a start condition and ended with a stop condition. The
first byte after a start condition is always the slave device address byte. If this is
the device’s own address, the device will generate an acknowledge by pulling the
SID line low during the ninth clock pulse, then accept the data in subsequent
bytes (auto-incrementing the subaddress) until another stop condition is detected.
The eighth bit of the address byte is the read/write bit (high = read from
addressed device; low = write to the addressed device). Data bytes are always
acknowledged during the ninth clock pulse by the addressed device.
NOTE: During the acknowledge period, the transmitting device must leave the SID
line high.
Premature termination of the data transfer is allowed by generating a stop
condition at any time. When this happens, the CX25870/871 will remain in the
state defined by the last complete data byte transmitted and any master
acknowledge subsequent to reading the chip ID (subaddress 0x89 if ALTADDR
pin is 0) is ignored.
The maximum serial interface speed for the CX25870/871 is 400 kHz.
100381B
Conexant
3-33
CONEXANT [ CONEXANT SYSTEMS, INC ]
