CX11656 HomePlug 1.0 PHY Data Sheet
3.5
SPI Master Interface
The SPI Master interface gives the system designer the option of providing the CX11656
with the necessary configuration information from a simple, SPI-controlled EEPROM as
opposed to supplying this information via MAC management frames (transmitted over
the MII interface). The information stored in the EEPROM is intended to initialize the
CX11656 with specific information that will not be changed throughout its normal course
of operation. For specific features that require real-time control, this information must be
provided via the MAC management frames and not from the EEPROM.
The EEPROM must be an Atmel AT93C46, or equivalent, programmed in 8-bit mode.
3.5.1
SPI Master Interface Timing
The SPI Master interface signal timing is illustrated in Figure 3-23.
Figure 3-23. SPI Master Interface Signal Timing Diagram
tSPI_HIGH
tSPI_SU
SPIS_CLK
tSPI_LOW
tSPI_H
SPIS_DI
DATA
tSPI_DIVD
tSPI_CSDV
SPIS_DO
DATA
tSPI_CSL
SPIS_CS_N
102069_027
3.5.2
SPI Master Interface DC Characteristics
The SPI Master interface DC characteristics are listed in Table 3-11.
Table 3-11. SPI Master Interface DC Characteristics
Parameter
Symbol
Parameter Name
SPI_SCLK Frequency
SPI_SCLK High Time
SPI_SCLK Low Time
SPI_DI Valid Output Delay from SPI_SCLK
SPI_CS Valid Output Delay from SPI_SCLK
SPI_CS Low Time
SPI_DO Setup Time to SPI_SCLK
SPI_DO Hold Time to SPI_SCLK
Test Condition
Min
Max
Unit
tSPI_F
6.125
90
90
15
15
MHz
ns
ns
ns
ns
ns
ns
ns
tSPI_HIGH
tSPI_LOW
tSPI_DIVD
tSPI_CSVD
tSPI_CSL
tSPI_SU
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
70
70
0
0
1000
50
0
tSPI_H
102069A
Conexant Proprietary and Confidential Information
3-21
CONEXANT [ CONEXANT SYSTEMS, INC ]
