AccessRunner ADSL-USB Modem Device Set Data Sheet
Table 3-7. CX11627 ADDP Hardware Signal Definitions
Signal Name
Pin
I/O
I/O Type
Signal Name/Description
CLOCK INTERFACE
Master Clock In. Connect to 35.328 MHz voltage controlled crystal
oscillator (VCXO) output through 51 Ω.
MCLK
68
66
I
I
VCXO Control Out. Oversampled VCXO analog control voltage
VXCO_CTRL
O
O
output. Connect to VCXO control circuit.
CX20431 AFE INTERFACE
Receive Data Lines. In the serial mode of operation, RX8 and RX0
transfer data from the AFE into the ADDP. The negative edge of the
AFE_STR# strobe signal from the AFE clocks the data into the
ADDP.
RX[15:0]
150-144, 142-
141, 138-135,
130-129
I
I
In the parallel mode of operation, RX[15:0] input data lines transfer
receive data into the ADDP. Data is clocked into the ADDP by
ADC_CLK. This mode is not used; leave RX[15:9] and RX[7:1] open.
Transmit Data Lines. In the serial mode of operation, TX15 (used as
a programmable width serial bus) transfers data to the AFE from the
ADDP. The negative edge of the AFE_STR# strobe signal from the
AFE clocks the data from the ADDP.
TX[15:0]
174-169, 166-157
O
O
In the parallel mode of operation, TX[15:0] output data lines transfer
data out of the ADDP. Data is clocked out of the ADDP by DAC_CLK.
This mode is not used; leave TX[14:0] open.
AFE Strobe. In the serial mode of operation, AFE_STR# from the
AFE triggers the transfer of serial transmit data on TX15 from the
ADDP to the AFE and triggers the transfer of serial receive data on
RX8 and RX0 from the AFE to the ADDP.
AFE_STR#
I
I
Receive Clock for Parallel Mode. In the parallel mode of operation,
data on RX[15:0] is clocked in to the ADDP by ADC_CLK. Not used;
leave open.
ADC_CLK
DAC_CLK
FILTER_CLK
128
2
O
O
O
O
O
O
Transmit Clock for Parallel Mode. In the parallel mode of operation,
data on TX[15:0] is clocked out of the ADDP by DAC_CLK. Not used;
leave open.
AFE Filter Clock. This signal can be used by the DAC interface block
3
to strobe the external AFE filters. Not use; leave open
P5200 UIC PARALLEL INTERFACE
Data Bus. A 16-bit input/output data bus used to send data to the UIC
during a read operation or receive data from the UIC during a write
operation. Connect to D[15:0] to UIC HAD[15:0], respectively.
D[15:0]
A[9:0]
104, 111-120,
123-127
I/O
I
It/Ot
Address Bus. A 10-bit input address bus that identifies the location in
the ADDP that data on D[15:0] is written to during a write operation, or
that data is read from during a read operation for placing on D[15:0].
Connect A[9:7] to UIC HC[18:16], respectively and A[6:0] to UIC
HC[07:01], respectively.
91, 94-102
It
Chip Select. Active low control input selects the ADDP. Connect CS#
to UIC HC12.
CS#
RD#
87
86
I
I
It
It
Data Read Enable. Active low control input strobes (on the negative
edge) data from the addressed location in the ADDP onto D[15:0].
Connect RD# to UIC HC08.
Data Write Enable. Active low control input strobes (on the negative
edge) data on D[15:0] into the ADDP addressed location. Connect
WR# to UIC HC09.
WR#
90
I
It
Conexant
100427B
3-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
