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CN8478EPF 参数 Datasheet PDF下载

CN8478EPF图片预览
型号: CN8478EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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7.0 Electrical and Mechanical Specifications  
CN8478/CN8474A/CN8472A/CN8471A  
7.2 Timing and Switching Specifications  
Multichannel Synchronous Communications Controller (MUSYCC™)  
7.2.4 EBUS Arbitration Timing  
Illustrated in Figures 7-13 and 7-14 are Intel- and Motorola-style write and read  
transactions.  
Figure 7-13. EBUS Write/Read Transactions, Intel-Style  
1
2
3
4
5
6
7
8
9
10  
See Notes  
ECLK  
HOLD  
HLDA  
Address  
Data  
EAD[31:0]  
EBE[3:0]*  
ALE  
Byte Enables from PCI Data Phase  
RD* (write)  
WR* (write)  
RD* (read)  
WR* (read)  
ALAPSE = 0  
ELAPSE = 0  
BLAPSE = 0  
8478_035  
NOTE(S):  
1. HLDA assertion depends on the external bus arbiter. While HOLD and HLDA are both deasserted, MUSYCC places shared  
EBUS signals in high impedance (three-state, shown as dashed lines).  
2. MUSYCC outputs valid command bus signals: EBE, ALE, RD*, and WR* 1 ECLK cycle after HLDA assertion.  
3. MUSYCC outputs valid EAD address signals, 2 ECLK cycles after HLDA assertion.  
4. ALE assertion occurs 3 ECLK cycles after HOLD and HLDA are both asserted.ALAPSE inserts a variable number of ECLK  
cycles to extend ALE high pulse width and EAD address interval.  
5. EAD address remains valid for 1 ECLK cycle after ALE falling edge. During a write transaction, MUSYCC outputs valid EAD  
write data 1 ECLK prior to WR* assertion. During a read transaction, EAD data lines are inputs.  
6. ELAPSE inserts a variable number of ECLK cycles to extend RD*/WR* low pulse width and EAD data intervals. Read data  
inputs are sampled on ECLK rising edge coincident with RD* deassertion.  
7. EAD write data and EBE byte enables remain valid for 1 ECLK cycle after RD*/WR* deassertion.  
8. HOLD is deasserted, and the bus is parked (command bus deasserted, EAD tristate) 1 ECLK after RD* or WR* deassertion.  
The bus parked state ends when HLDA is deasserted, 1 ECLK after RD* or WR* deassertion.  
9. Command bus is unparked (three-stated) one ECLK after HLDA deassertion; two different unpark phases are shown,  
indicating the dependence on HLDA deassertion. If HLDA remained asserted until the next bus request, then command bus  
remains parked until 1 ECLK cycle following the next HOLD assertion. Warning: Whenever HLDA is deasserted, all shared  
EBUS signals are forced to three-state after 1 ECLK cycle, regardless of whether the EBUS transaction was completed.  
MUSYCC will not reissue or repeat such an aborted transaction.  
10. BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus request.  
7-14  
Conexant  
100660E