CN8478/CN8474A/CN8472A/CN8471A
5.0 Memory Organization
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2 Descriptors
Table 5-12. Port Configuration Descriptor
Bit
Field
Name
Value
Description
31:10
9
RSVD
TRITX
0
0
Reserved.
Transmit Three-state Enabled. When a channel group is enabled, but a time slot within
the group is not mapped via the Time Slot Map, the transmitter three-states the output
data signal.
1
Transmit Three-State Disabled. When a channel group is enabled, but a time slot within
the group is not mapped via the Time Slot Map, the transmitter outputs a logic 1 on the
output data signal.
8
7
ROOF_EDGE
0
1
0
Receiver Out of Frame—Falling Edge. ROOF input sampled in on falling edge of RCLK.
Receiver Out of Frame—Rising Edge.
RSYNC_EDGE
Receiver Frame Synchronization—Falling Edge. RSYNC input sampled in on falling
edge of RCLK.
1
0
1
0
Receiver Frame Synchronization—Rising Edge.
Receiver Data—Falling Edge. RDAT input sampled in on falling edge of RCLK.
Receiver Data—Rising Edge.
6
5
RDAT_EDGE
TSYNC_EDGE
Transmitter Frame Synchronization—Falling Edge. TSYNC input sampled in on falling
edge of TCLK.
1
0
1
0
0
1
2
3
4
Transmitter Frame Synchronization—Rising Edge.
Transmitter Data—Falling Edge. TDAT output latched out on falling edge of TCLK.
Transmitter Data—Rising Edge.
4
TDAT_EDGE
3
RSVD
Reserved.
2:0
PORTMD[2:0]
T1 Mode—24 time slots and T1 signaling.
E1 Mode—32 time slots and E1 signaling.
2xE1 Mode—64 time slots and E1 signaling.
4xE1 Mode—128 time slots and E1 signaling.
Nx64 Mode. Frame synchronization flywheel disabled. COFA detection disabled. Every
synchronization signal assertion resets time slot counter to zero.
5–7
Reserved.
100660E
Conexant
5-19